SH7263 Datasheet, PDF (1114/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
• Data buffering control
The CD-ROM decoder outputs data to the buffer area in a specific format where the sync code
is at the head of the data for each sector.
21.1.1 Formats Supported by ROM-DEC
The CD-ROM decoder of this LSI supports the five formats shown in figure 21.1.
Mode0
Sync
Header
(12 bytes) (4 bytes)
All 0
Mode1
Sync
Header
(12 bytes) (4 bytes)
Data (2048 bytes)
EDC
(4 bytes)
0
P-parity Q-parity
(8 bytes) (172 bytes) (104 bytes)
Mode2
Sync
Header
(not XA) (12 bytes) (4 bytes)
Data (2336 bytes)
Mode2
Form1
Sync
Header Sub-header
(12 bytes) (4 bytes) (8 bytes)
Mode2
Form2
Sync
Header Sub-header
(12 bytes) (4 bytes) (8 bytes)
Data (2048 bytes)
Data (2324 bytes)
EDC
P-parity Q-parity
(4 bytes) (172 bytes) (104 bytes)
EDC
(4 bytes)
Figure 21.1 Formats Supported by ROM-DEC
Rev. 2.00 Mar. 14, 2008 Page 1080 of 1824
REJ09B0290-0200