SH7263 Datasheet, PDF (1606/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
32.2.11 Deep Standby Control Register 2 (DSCTR2)
DSCTR2 is an 8-bit readable/writable register that controls the state of the external bus control
pins and specifies the startup method when returning from deep standby mode. Only byte access is
valid.
Note: When writing to this register, see section 32.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
CS0 RAM
KEEPE BOOT
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R
R
R
R
R
R
Bit
7
6
5 to 0
Initial
Bit Name Value
CS0KEEPE 0
RAMBOOT 0
⎯
All 0
R/W Description
R/W Retention of External Bus Control Pin State
0: The state of the external bus control pins is not
retained when returning from deep standby mode.
1: The state of the external bus control pins is
retained when returning from deep standby mode.
R/W Selection of Startup Method After Return from Deep
Standby Mode
If deep standby mode is canceled by the MRES, NMI,
or IRQ bit, the program counter (PC) and the stack
pointer (SP) are read from the following addresses,
respectively, in the power-on reset exception
handling.
0: Addresses H'00000000 and H'00000004
1: Addresses H'FFFF8000 and H'FFFF8004
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1572 of 1824
REJ09B0290-0200