SH7263 Datasheet, PDF (1101/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

20.5.2 Master Transmission
Figure 20.9 shows the flowchart for master transmission.
START
Initial setting
Section 20 IEBus^TM Controller (IEB)
[IESA1, IESA2 register setting]
Slave address
[IEMCR register setting]
Broadcast/normal selection
Retransfer counts
Control bits
[IETBFL register setting]
Message length bits
[IETB001 to IETB128 setting]
Transmit data
[IECMR register setting]
Master communications
request command
Transmit start interrupt
Transmit error interrupt
(TXE***)
Transmit start interrupt (TXS)
Interrupt processing
IETSR[TXS] clear
Transmit completion
interrupt
Transmit error interrupt
(TXE***)
Transmit completion interrupt (TXF)
Interrupt processing
IETSR[TXF] clear
Interrupt processing
IETSR[TXE***] clear
END
Figure 20.9 Flowchart for Master Transmission
Rev. 2.00 Mar. 14, 2008 Page 1067 of 1824
REJ09B0290-0200