SH7263 Datasheet, PDF(1394/1862 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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SH7263 Datasheet, PDF (1394/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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Section 25 USB 2.0 Host/Function Module (USB)

25.4.10 Pipe Schedule

(1) Conditions for Generating a Transaction

When the host controller function is selected and UACT has been set to 1, this module generates a

transaction under the conditions noted in table 25.27.

Table 25.27 Conditions for Generating a Transaction

Conditions for Generation

Transaction

DIR

PID

IITV0

Buffer State SUREQ

Setup

Control transfer data stage,

status stage, bulk transfer

â¯*1

IN

OUT

Interrupt transfer

IN

OUT

â¯*1

BUF

BUF

BUF

BUF

â¯*1

Invalid

Invalid

Valid

Valid

â¯*1

Receive

area exists

Send data

exists

Receive

area exists

Send data

exists

1 setting

â¯*1

â¯*1

â¯*1

â¯*1

Isochronous transfer

IN

BUF

Valid

*2

â¯*1

OUT

BUF

Valid

*3

â¯*1

Notes: 1. Symbols (â¯) in the table indicate that the condition is one that is unrelated to the

generating of tokens. âValidâ indicates that, for interrupt transfers and isochronous

transfers, the condition is generated only in transfer frames that are based on the

interval counter. âInvalidâ indicates that the condition is generated regardless of the

interval counter.

2. This indicates that a transaction is generated regardless of whether or not there is a

receive area. If there was no receive area, however, the received data is destroyed.

3. This indicates that a transaction is generated regardless of whether or not there is any

data to be sent. If there was no data to be sent, however, a zero-length packet is sent.

Rev. 2.00 Mar. 14, 2008 Page 1360 of 1824

REJ09B0290-0200

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