SH7263 Datasheet, PDF (1850/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Initial values of general registers.............. 45
Initial values of system registers............... 45
Instruction features ................................... 48
Instruction format ..................................... 57
Instruction set ........................................... 61
Integer division instructions ................... 135
Internal arbitration for transmission ....... 987
Interrupt controller (INTC)..................... 141
Interrupt exception handling................... 132
Interrupt exception handling vectors
and priorities........................................... 160
Interrupt priority level ............................ 131
Interrupt response time ........................... 174
Interrupt transfers ................................. 1350
IREADY interrupt ................................ 1145
IRQ interrupts......................................... 156
ISEC interrupt....................................... 1144
Isochronous transfers............................ 1351
ISY interrupt......................................... 1145
ITARG interrupt ................................... 1144
J
Jump table base register (TBR) ................ 43
L
LCD controller (LCDC) ....................... 1365
LCD module power-supply states ........ 1417
LCDC timing ........................................ 1760
Load-store architecture ............................. 48
Local acceptance filter mask (LAFM).... 922
Logic operation instructions ..................... 74
Low-frequency mode.............................. 344
Low-power SDRAM .............................. 349
LRU ........................................................ 213
M
Mailbox .......................................... 909, 913
Mailbox configuration ............................ 921
Mailbox control ...................................... 909
Manual reset ........................................... 126
Rev. 2.00 Mar. 14, 2008 Page 1816 of 1824
REJ09B0290-0200
Master receive operation......................... 847
Master transmit operation ....................... 845
Memory-mapped cache........................... 226
Message control field.............................. 918
Message data fields................................. 923
Message receive sequence .................... 1001
Message transmission request......... 987, 996
Micro processor interface (MPI)............. 909
Module standby function ...................... 1589
Module standby mode setting ................. 823
MPX-I/O interface .................................. 304
MTU2 functions...................................... 442
MTU2 interrupts ..................................... 591
MTU2 output pin initialization ............... 622
MTU2 timing ........................................ 1738
Multi mode............................................ 1163
Multi-function timer pulse unit 2
(MTU2)................................................... 441
Multiplexed pins (port A) ..................... 1455
Multiplexed pins (port B)...................... 1455
Multiplexed pins (port C)...................... 1456
Multiplexed pins (port D) ..................... 1457
Multiplexed pins (port E)...................... 1458
Multiplexed pins (port F) ...................... 1460
Multiply and accumulate register high
(MACH).................................................... 44
Multiply and accumulate register low
(MACL) .................................................... 44
Multiply/Multiply-and-accumulate
operations.................................................. 49
N
NMI interrupt.......................................... 156
Noise filter .............................................. 857
Non-compressed modes .......................... 885
Nonlinearity error ................................. 1172
Non-numbers (NaN) ................................. 91
Normal space interface ........................... 296
Note on using a PLL oscillation
circuit ...................................................... 114