SH7263 Datasheet, PDF (79/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.1.4 Register Banks
For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and
system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried
out using a register bank. The register contents are automatically saved in the bank after the CPU
accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a
RESBANK instruction in an interrupt processing routine.
This LSI has 15 banks. For details, see the SH-2A, SH2A-FPU Software Manual and section 6.8,
Register Banks.
2.1.5 Initial Values of Registers
Table 2.1 lists the values of the registers after a reset.
Table 2.1 Initial Values of Registers
Classification
General registers
Register
R0 to R14
R15 (SP)
Control registers
SR
System registers
GBR, TBR
VBR
MACH, MACL, PR
PC
Initial Value
Undefined
Value of the stack pointer in the vector
address table
Bits I[3:0] are 1111 (H'F), BO and CS are
0, reserved bits are 0, and other bits are
undefined
Undefined
H'00000000
Undefined
Value of the program counter in the vector
address table
Rev. 2.00 Mar. 14, 2008 Page 45 of 1824
REJ09B0290-0200