SH7263 Datasheet, PDF (157/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 5 Exception Handling
5.2 Resets
5.2.1 Input/Output Pins
Table 5.5 shows the reset-related pin configuration.
Table 5.5 Pin Configuration
Pin Name
Symbol
Power-on reset RES
I/O
Input
Manual reset MRES
Input
Function
When this pin is driven low, this LSI shifts to the power-
on reset processing
When this pin is driven low, this LSI shifts to the manual
reset processing.
5.2.2 Types of Reset
A reset is the highest-priority exception handling source. There are two kinds of reset, power-on
and manual. As shown in table 5.6, the CPU state is initialized in both a power-on reset and a
manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip
peripheral module registers except a few registers are also initialized by a power-on reset, but not
by a manual reset.
Table 5.6 Reset States
Conditions for Transition to Reset State
Internal States
Type
RES H-UDI Command MRES WDT Overflow CPU
Other Modules
Power-on Low —
—
—
reset
High H-UDI reset assert —
—
command is set
Initialized
Initialized
Initialized
Initialized
High Command other —
Power-on reset Initialized
*
than H-UDI reset
assert is set
Manual High Command other Low —
reset
than H-UDI reset
assert is set
Initialized
*
High Command other High Manual reset Initialized
*
than H-UDI reset
assert is set
Note: * See section 34.3, Register States in Each Operating Mode.
Rev. 2.00 Mar. 14, 2008 Page 123 of 1824
REJ09B0290-0200