SH7263 Datasheet, PDF (41/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Items
IEBus^TM controller
(IEB)
Note:
IEB is included or not
depending on the
product code.
CD-ROM decoder
(ROM-DEC)
Specification
• IEBus protocol control (layer 2) supported
⎯ Half-duplex asynchronous communications
⎯ Multi-master system
⎯ Broadcast communications function
⎯ Selectable mode (three types) with different transfer speeds
• On-chip buffers (dual port RAM) for data transmission and reception
that enable up to 128 bytes of consecutive transmit/reception
(maximum number of transfer bytes in mode 2)
• Operating frequency
⎯ 12 MHz, 12.58 MHz
(IEB uses 1/2 divided clocks of Pφ, AUDIO_X1, or AUDIO_X2.)
⎯ 18 MHz, 18.87 MHz
(IEB uses 1/3 divided clocks of Pφ, AUDIO_X1, or AUDIO_X2.)
⎯ 24 MHz, 25.16 MHz
(IEB uses 1/4 divided clocks of Pφ, AUDIO_X1, or AUDIO_X2.)
⎯ 30 MHz, 31.45 MHz
(IEB uses 1/5 divided clocks of Pφ, AUDIO_X1, or AUDIO_X2.)
⎯ 36 MHz, 37.74 MHz
(IEB uses 1/6 divided clocks of AUDIO_X1 or AUDIO_X2.)
• Support of five formats: mode 0, mode 1, mode 2, mode 2 form 1, and
mode 2 form 2
• Sync codes detection and protection
(Protection: When a sync code is not detected, it is automatically
inserted.)
• Descrambling
• ECC correction
⎯ P, Q, PQ, and QP correction
⎯ PQ or QP correction can be repeated up to three times
• EDC check
Performed before and after ECC
• Mode and form are automatically detected
• Link sectors are automatically detected
• Buffering data control
Buffering CD-ROM data including Sync code is transferred in specified
format, after the data is descrambled, corrected by ECC, and checked
by EDC.
Rev. 2.00 Mar. 14, 2008 Page 7 of 1824
REJ09B0290-0200