SH7263 Datasheet, PDF (448/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
10.4 Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto request, external request, and on-chip
peripheral module request. In bus mode, the burst mode or the cycle steal mode can be selected.
10.4.1 Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation
register (DMAOR), three reload registers (RSAR, RDAR, RDMATCR) and DMA extension
resource selector (DMARS) are set for the target transfer conditions, the DMAC transfers data
according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TEMASK = 0 or 1 (TE = 0 when
TEMASK = 0), AE = 0, NMIF = 0).
2. When a transfer request comes and transfer is enabled, the DMAC transfers one transfer unit of
data (depending on the settings of the TS1 and TS0 bits). For an auto request, the transfer
begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented by 1 for each transfer. The actual transfer flows vary by address mode and bus
mode.
3. When half of the specified transfer count is exceeded (when DMATCR reaches half of the
initial value), an HEI interrupt is sent to the CPU if the HIE bit in CHCR is set to 1.
4. When transfer has been completed for the specified count (when DMATCR reaches 0) while
the TEMASK bit is 0, the transfer ends normally. If the IE bit in CHCR is set to 1 at this time,
a DEI interrupt is sent to the CPU. When DMATCR reaches 0 while the TEMASK bit is 1, the
TE bit is set to 1 and then the values set in RSAR, RDAR and RDMATCR are reloaded in
SAR, DAR and DMATCR, respectively to continue transfer operation until the DMA transfer
request is cancelled.
5. When an address error in the DMAC or an NMI interrupt is generated, the transfer is
terminated. Transfers are also terminated when the DE bit in CHCR or the DME bit in
DMAOR is cleared to 0.
Rev. 2.00 Mar. 14, 2008 Page 414 of 1824
REJ09B0290-0200