SH7263 Datasheet, PDF (1261/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
24.5 Interrupt Sources
The FLCTL has six interrupt sources: Status error, ready/busy timeout error, ECC error, transfer
end, FIFO0 transfer request, and FIFO1 transfer request. Each of the interrupt sources has its
corresponding interrupt flag and the interrupt can be requested independently to the CPU if the
interrupt is enabled by the interrupt enable bit. Note that the status error, ready/busy timeout error,
and ECC error use the common FLSTE interrupt to the CPU.
Table 24.5 FLCTL Interrupt Requests
Interrupt Source
FLSTE interrupt
FLTEND interrupt
FLTRQ0 interrupt
FLTRQ1 interrupt
Interrupt Flag
STERB
BTOERB
ECERB
TREND
TRREQF0
TRREQF1
Enable Bit
STERINTE
RBERINTE
ECERINTE
TEINTE
TRINTE0
TRINTE1
Description
Status error
Ready/busy timeout error
ECC error
Transfer end
FIFO0 transfer request
FIFO1 transfer request
Priority
Highest
Lowest
Rev. 2.00 Mar. 14, 2008 Page 1227 of 1824
REJ09B0290-0200