SH7263 Datasheet, PDF (544/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.27 Timer Buffer Transfer Set Register (TBTER)
TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer
registers* used in complementary PWM mode to the temporary registers and specifies whether to
link the transfer with interrupt skipping operation. The MTU2 has one TBTER.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
BTE[1:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 2 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1, 0 BTE[1:0] 00
R/W These bits enable or disable transfer from the buffer
registers* used in complementary PWM mode to the
temporary registers and specify whether to link the
transfer with interrupt skipping operation.
For details, see table 11.40.
Note: * Applicable buffer registers:
TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR
Rev. 2.00 Mar. 14, 2008 Page 510 of 1824
REJ09B0290-0200