SH7263 Datasheet, PDF (1372/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
The operation conditions for the TRCLR bit are as noted below.
• If the transactions are being counted and PID = BUF, the current counter cannot be cleared.
• If there is any data left in the buffer, the current counter cannot be cleared.
(f) FIFO Port Access Wait Specification
Access to FIFO ports in this module has the following restrictions.
• Do not exceed a transfer speed of 48 MB/s.
This module can limit access cycle through the access wait set (FWAIT) bit so that the peripheral
clock frequency is not limited.
The FWAIT bit can be set to each FIFO port, and can be efficiently set according to the CPU
speed, the transfer source access cycle, and so on.
• Conditions
Access direction: writing to FIFO
Peripheral clock frequency: 66 MHz
MBW bit setting value: 10 (32-bit width)
Access type: After transfer data is read from the on-chip memory (the source), it is written to
the FIFO port. In this case, 2 clock cycles are required for source access.
• Example of calculation
(2 + (FWAIT + 2)) × 1/66 MHz ≥ 1/48 MHz × 4 (32 bits)
FWAIT = 2 (4 clock cycles)
(g) Methods of Accessing FIFO Port for Fractional-Width Data
If a unit of data narrower than the bit width specified by the MBW bits in the FIFO port select
register is to be read from a FIFO port, read the data with the bit width specified by the MBW bits
and then use software to discard the unnecessary data.
If a unit of data narrower than the bit width specified by the MBW bits in the FIFO port select
register is to be written to a FIFO port, access the FIFO port as shown in the example below. The
example shows how to write 24-bit-wide data when the FIFO port width has been specified as 32
bits (MBW = 10).
Rev. 2.00 Mar. 14, 2008 Page 1338 of 1824
REJ09B0290-0200