SH7263 Datasheet, PDF (698/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 12 Compare Match Timer (CMT)
12.5 Usage Notes
12.5.1 Conflict between Write and Compare-Match Processes of CMCNT
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 12.5 shows
the timing to clear the CMCNT counter.
Peripheral clock
(Pφ)
Address signal
Internal write signal
CMCSR write cycle
T1
T2
CMCNT
Counter clear signal
CMCNT
N
H'0000
Figure 12.5 Conflict between Write and Compare Match Processes of CMCNT
Rev. 2.00 Mar. 14, 2008 Page 664 of 1824
REJ09B0290-0200