SH7263 Datasheet, PDF (927/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
• Transmitting and Receiving in the Order of Padding Bits and Serial Data; with Delay
As basic sample format configuration except SDTA = 1
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA _{TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0}
Figure 18.14 Transmitting and Receiving in the Order of Padding Bits and Serial Data;
with Delay
• Transmitting and Receiving in the Order of Padding Bits and Serial Data; without Delay
As basic sample format configuration except SDTA = 1 and DEL = 1
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA _{TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 0}
Figure 18.15 Transmitting and Receiving in the Order of Padding Bits and Serial Data;
without Delay
• Transmitting and Receiving in the Order of Serial Data and Padding Bits; without Delay
As basic sample format configuration except DEL = 1
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA 0 0 TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31 TD30
Figure 18.16 Transmitting and Receiving in the Order of Serial Data and Padding Bits;
without Delay
Rev. 2.00 Mar. 14, 2008 Page 893 of 1824
REJ09B0290-0200