SH7263 Datasheet, PDF (1012/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
Bit 15 to 0 — Timer Compare Match Register (TCMR2): Indicates the value of CYCTR when
compare match occurs.
(10) Tx-Trigger Time Selection Register (TTTSEL)
This register is a 16-bit read/write register and specifies the Tx-Trigger Time waiting for compare
match with Cycle Time. Only one bit is allowed to be set. Please don't set more bits than one, or
clear all bits.
This register may only be modified during configuration mode. The modification algorithm is
shown in figure 19.13.
Please note that this register is only indented for test and diagnosis. When not in test mode, this
register must not be written to and the returned value is not guaranteed.
• TTTSEL (Address = H'0A4)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
TTTSEL[14:8]
-
-
-
-
-
-
-
-
Initial value: 0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R/W R/W R/W R/W R/W R/W R
R
R
R
R
R
R
R
Note: Only one bit is allowed to be set.
Bit 15: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 14 to 8 — Specifies the Tx-Trigger Time waiting for compare match with CYCTR The bit 14
to 8 corresponds to Mailbox-30 to 24, respectively.
Bits 7 to 0: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Rev. 2.00 Mar. 14, 2008 Page 978 of 1824
REJ09B0290-0200