SH7263 Datasheet, PDF (1156/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.44 Automatic Buffering Start Sector Setting: Frames Control Register (CBUFCTL3)
The automatic buffering start sector setting: frames control register (CBUFCTL3) indicates the
frames (1 frame = 1/75 second) value in the header for the first sector to be buffered
Bit: 7
Initial value: 0
R/W: R/W
6
0
R/W
5
0
R/W
4
3
BS_FRM[7:0]
0
0
R/W R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
7 to 0
Bit Name
BS_FRM[7:0]
Initial
Value
All 0
R/W Description
R/W Indicate setting of the frames (1/75 second) value in the
header for the first sector to be buffered.
Rev. 2.00 Mar. 14, 2008 Page 1122 of 1824
REJ09B0290-0200