SH7263 Datasheet, PDF (86/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.3.2 Addressing Modes
Addressing modes and effective address calculation are as follows:
Table 2.8 Addressing Modes and Effective Addresses
Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
Register direct Rn
The effective address is register Rn. (The operand —
is the contents of register Rn.)
Register indirect @Rn
The effective address is the contents of register Rn. Rn
Rn
Rn
Register indirect @Rn+
with post-
increment
The effective address is the contents of register Rn. Rn
A constant is added to the contents of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
(After
instruction
execution)
Byte:
Rn
Rn
Rn + 1 → Rn
Rn + 1/2/4 ₊
Word:
Rn + 2 → Rn
1/2/4
Longword:
Rn + 4 → Rn
Register indirect @-Rn
with pre-
decrement
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
Rn
Rn – 1/2/4 _–
Rn – 1/2/4
1/2/4
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction is
executed with
Rn after this
calculation)
Rev. 2.00 Mar. 14, 2008 Page 52 of 1824
REJ09B0290-0200