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SH7263 Datasheet, PDF (129/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Section 3 Floating-Point Unit (FPU)
Initial
Bit
Bit Name Value R/W
17 to 12 Cause
All 0 R/W
11 to 7 Enable All 0 R/W
6 to 2 Flag
All 0 R/W
1
RM1
0
R/W
0
RM0
1
R/W
Description
FPU Exception Cause Field
FPU Exception Enable Field
FPU Exception Flag Field
The FPU exception source field is initially cleared to 0
when a floating-point operation instruction is executed.
When an FPU exception is generated by a floating-
point operation, the corresponding bits in the FPU
exception source field and FPU exception flag field are
set to 1. The FPU exception flag field bit remains set to
1 until it is cleared to 0 by software. FPU exception
handling occurs if the corresponding bit in the FPU
exception enable field is set to 1.
For bit allocations of each field, see table 3.3.
Rounding Mode
These bits select the rounding mode.
00: Round to Nearest
01: Round to Zero
10: Reserved
11: Reserved
Table 3.3 Bit Allocation for FPU Exception Handling
Field Name
FPU
Invalid
Division Overflow Underflow Inexact
Error (E) Operation (V) by Zero (Z) (O)
(U)
(I)
Cause
FPU exception
cause field
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Enable
FPU exception
enable field
None
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Flag
FPU exception flag None
Bit 6
field
Bit 5
Note: No FPU error occurs in the SH2A-FPU.
Bit 4
Bit 3
Bit 2
3.3.3 Floating-Point Communication Register (FPUL)
Information is transferred between the FPU and CPU via FPUL. FPUL is a 32-bit system register
that is accessed from the CPU side by means of LDS and STS instructions. For example, to
convert the integer stored in general register R1 to a single-precision floating-point number, the
processing flow is as follows:
R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1
Rev. 2.00 Mar. 14, 2008 Page 95 of 1824
REJ09B0290-0200