SH7263 Datasheet, PDF (1102/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
20.5.3 Slave Reception
Figure 20.10 shows the flowchart for slave reception.
START
Initial setting
Receive start interrupt
Receive error interrupt
(RXE***)
Receive start interrupt (RXS)
Interrupt processing
IERSR[RXS] clear
Receive completion
interrupt
Receive error interrupt
(RXE***)
Receive completion interrupt (RXF)
Interrupt processing
IERSR[RXF] clear
Receive data read
(IERB001 to IERB128)
IERSR[RXBSY] clear
Interrupt processing
IERSR[RXE***] clear
END
Figure 20.10 Flowchart for Slave Reception
Rev. 2.00 Mar. 14, 2008 Page 1068 of 1824
REJ09B0290-0200