SH7263 Datasheet, PDF (1283/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
25.3.7 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)
CFIFOSEL, D0FIFOSEL and D1FIFOSEL are registers that assign the pipe to the FIFO port, and
control access to the corresponding port.
The same pipe should not be specified by the CURPIPE bits in CFIFOSEL, D0FIFOSEL and
D1FIFOSEL. When the CURPIPE bits in D0FIFOSEL and D1FIFOSEL are cleared to B'000, no
pipe is selected.
The pipe number should not be changed while the DMA transfer is enabled.
These registers are initialized by a power-on reset or a software reset.
(1) CFIFOSEL
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RCNT REW -
-
MBW[1:0]
-
-
-
-
ISEL
-
-
CURPIPE[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W*¹ R
R R/W R/W R
R
R
R R/W R
R R/W R/W R/W
Bit
Bit Name
15
RCNT
14
REW
13, 12 ⎯
Initial
Value
0
0
All 0
R/W Description
R/W Read Count Mode
0: The DTLN bit is cleared when all of the receive
data has been read.
1: The DTLN bit is decremented when the receive
data is read.
R/W*¹ Buffer Pointer Rewind
0: Invalid
1: The buffer pointer is rewound.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1249 of 1824
REJ09B0290-0200