SH7263 Datasheet, PDF (1849/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

DMA transfer flowchart ......................... 415
DMAC activation ................................... 593
DMAC interface ................................... 1006
DMAC timing....................................... 1737
DREQ pin sampling timing .................... 434
DTCH interrupt..................................... 1321
Dual address mode.................................. 426
E
ECC code.............................................. 1224
ECC correction function ....................... 1138
ECC error check ................................... 1224
EDC check function.............................. 1138
Effective address calculation .................... 52
Electrical characteristics ....................... 1683
Endian..................................................... 289
Endian conversion for data
in the input stream ................................ 1132
Equation for getting SCBRR value......... 736
Example of time triggered system .......... 997
Exception handling ................................. 117
Exception handling state........................... 85
Exception handling vector table ............. 121
Exception source generation immediately
after delayed branch instruction.............. 137
Exceptions triggered by instructions....... 133
External request mode ............................ 416
External trigger input timing ................ 1170
F
Fixed mode ............................................. 422
FLCTL interrupt requests ..................... 1227
FLCTL timing....................................... 1750
Floating point operation instructions ...... 136
Floating-point exceptions ......................... 97
Floating-point format................................ 88
Floating-point operation instructions........ 79
Floating-point ranges ................................ 90
Floating-point registers............................. 93
Floating-point unit (FPU) ......................... 87
Flow of the user break operation............. 202
Format of double-precision
floating-point number ............................... 88
Format of single-precision
foating-point number ................................ 88
FPU exception handling............................ 97
FPU exception sources.............................. 97
FPU-related CPU instructions................... 81
Frame update interrupt.......................... 1319
Full-scale error ...................................... 1172
G
General illegal instructions ..................... 135
General registers ....................................... 41
Global base register (GBR)....................... 43
H
Halt mode................................................ 983
H-UDI commands................................. 1596
H-UDI interrupt ............................ 156, 1599
H-UDI reset........................................... 1599
H-UDI timing........................................ 1764
I
I/O port timing ...................................... 1763
I/O ports ................................................ 1519
I²C bus format ......................................... 844
I²C bus interface 3 (IIC3)........................ 825
IBUF interrupt....................................... 1145
ID reorder................................................ 931
IEBus bit format.................................... 1027
IEBus communications protocol ........... 1012
IEBus™ controller (IEB) ...................... 1011
IERR interrupt....................................... 1145
IIC3 timing............................................ 1744
Immediate data.......................................... 50
Immediate data accessing.......................... 50
Immediate data format .............................. 47
Influences on absolute precision ........... 1176
Initial values of control registers............... 45
Rev. 2.00 Mar. 14, 2008 Page 1815 of 1824
REJ09B0290-0200