SH7263 Datasheet, PDF (1404/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
Bit
13, 12
Initial
Bit Name Value R/W
ICKSEL[1:0] 00
R/W
11 to 9 ⎯
All 0 R
8
⎯
1
R
7, 6
⎯
All 0 R
5 to 0 DCDR[5:0] 000001 R/W
Description
Input Clock Select
Set the clock source for DOTCLK.
00: Bus clock is selected
01: Peripheral clock is selected
10: External clock is selected
11: Setting prohibited
Reserved
These bits are always read as 0. The write value should
always be 0.
Reserved
This bit is always read as 1. The write value should
always be 1.
Reserved
These bits are always read as 0. The write value should
always be 0.
Clock Division Ratio
Set the input clock division ratio. For details on the
setting, see table 26.3.
Table 26.3 I/O Clock Frequency and Clock Division Ratio
DCDR[5:0]
Clock Division
Ratio
50.000
I/O Clock Frequency (MHz)
60.000
66.000
000001
1/1
50.000
60.000
66.000
000010
1/2
25.000
30.000
33.000
000011
1/3
16.667
20.000
22.000
000100
1/4
12.500
15.000
16.500
000110
1/6
8.333
10.000
11.000
001000
1/8
6.250
7.500
8.250
001100
1/12
4.167
5.000
5.500
010000
1/16
3.125
3.750
4.125
011000
1/24
2.083
2.500
2.750
100000
1/32
1.563
1.875
2.063
Note: Any setting other than above is handled as a clock division ratio of 1/1 (initial value).
Rev. 2.00 Mar. 14, 2008 Page 1370 of 1824
REJ09B0290-0200