SH7263 Datasheet, PDF (12/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

6.4.6 On-Chip Peripheral Module Interrupts ................................................................. 158
6.5 Interrupt Exception Handling Vector Table and Priority................................................... 159
6.6 Operation ........................................................................................................................... 170
6.6.1 Interrupt Operation Sequence ............................................................................... 170
6.6.2 Stack after Interrupt Exception Handling ............................................................. 173
6.7 Interrupt Response Time.................................................................................................... 174
6.8 Register Banks ................................................................................................................... 180
6.8.1 Banked Register and Input/Output of Banks ........................................................ 181
6.8.2 Bank Save and Restore Operations....................................................................... 181
6.8.3 Save and Restore Operations after Saving to All Banks....................................... 183
6.8.4 Register Bank Exception ...................................................................................... 184
6.8.5 Register Bank Error Exception Handling ............................................................. 184
6.9 Data Transfer with Interrupt Request Signals.................................................................... 185
6.9.1 Handling Interrupt Request Signals as Sources
for CPU Interrupt but Not DMAC Activating ...................................................... 186
6.9.2 Handling Interrupt Request Signals as Sources
for Activating DMAC but Not CPU Interrupt ...................................................... 186
6.10 Usage Note......................................................................................................................... 187
6.10.1 Timing to Clear an Interrupt Source ..................................................................... 187
6.10.2 Timing of IRQOUT Negation............................................................................... 187
Section 7 User Break Controller (UBC)............................................................ 189
7.1 Features.............................................................................................................................. 189
7.2 Input/Output Pin ................................................................................................................ 191
7.3 Register Descriptions......................................................................................................... 192
7.3.1 Break Address Register (BAR)............................................................................. 193
7.3.2 Break Address Mask Register (BAMR) ............................................................... 194
7.3.3 Break Data Register (BDR) .................................................................................. 195
7.3.4 Break Data Mask Register (BDMR)..................................................................... 196
7.3.5 Break Bus Cycle Register (BBR) ......................................................................... 197
7.3.6 Break Control Register (BRCR) ........................................................................... 199
7.4 Operation ........................................................................................................................... 202
7.4.1 Flow of the User Break Operation ........................................................................ 202
7.4.2 Break on Instruction Fetch Cycle ......................................................................... 203
7.4.3 Break on Data Access Cycle................................................................................. 204
7.4.4 Value of Saved Program Counter ......................................................................... 205
7.4.5 Usage Examples.................................................................................................... 206
7.5 Usage Notes ....................................................................................................................... 209
Rev. 2.00 Mar. 14, 2008 Page xii of xxxiv
REJ09B0290-0200