SH7263 Datasheet, PDF (135/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows:
(1) Crystal Oscillator
The crystal oscillator is an oscillation circuit in which the crystal resonator is connected to the
XTAL/EXTAL pin or USB_X1/USB_X2 pin. This can be used according to the clock operating
mode.
(2) Divider 1
Divider 1 divides the frequency of the clock from the EXTAL pin, the CKIO pin, and the
USB_X1 pin. The division ratio depends on the clock operating mode.
(3) PLL Circuit
PLL circuit multiplies the frequency of input clock from the crystal oscillator/the EXTAL pin, the
CKIO pin or the USB_X1 pin by 8, 12, or 16. The multiplication rate is set by the frequency
control register. When this is done, the phase of the rising edge of the internal clock is controlled
so that it will agree with the phase of the rising edge of the CKIO pin.
The input clock to be used depends on the clock operating mode. The clock operating mode is
specified using the MD_CLK0 and MD_CLK1 pins. For details on the clock operating mode, see
table 4.2.
(4) Divider 2
Divider 2 generates a clock signal whose operating frequency can be used for the internal clock or
the peripheral clock. The operating frequency can be 1, 1/2, 1/3, 1/4, 1/6, 1/8 or 1/12 times the
output frequency of the PLL circuit, and it should not be lower than the clock frequency on the
CKIO pin. The division ratio is set by the frequency control register.
(5) Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency using the MD_CLK0 and
MD_CLK1 pins and the frequency control register (FRQCR).
Rev. 2.00 Mar. 14, 2008 Page 101 of 1824
REJ09B0290-0200