SH7263 Datasheet, PDF (1620/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
• Canceling by an interrupt
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling
edge or rising edge of an IRQ pin (IRQ7 to IRQ0 assigned to PE11 to PE4) (selected by the
IRQn sense select bits (IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the
interrupt controller (INTC)) is detected, clock oscillation is started after the wait time for the
oscillation settling time. After the oscillation settling time has elapsed, deep standby mode is
cancelled and the power-on reset exception handling is executed.
The clock output phase of the CKIO pin may be unstable immediately after detecting an
interrupt and until deep standby mode is canceled. When deep standby mode is canceled by the
falling edge of the NMI pin, the NMI pin should be high when the CPU enters deep standby
mode (when the clock pulse stops) and should be low when deep standby mode is canceled
(when the clock is initiated after oscillation settling). When deep standby mode is canceled by
the rising edge of the NMI pin, the NMI pin should be low when the CPU enters deep standby
mode (when the clock pulse stops) and should be high when deep standby mode is canceled
(when the clock is initiated after oscillation settling). (The same applies to the IRQ pin.)
• Canceling with a reset
When the RES pin is driven low, this LSI leaves deep standby mode and enters the power-on
reset state. After this, driving the RES pin high initiates power-on reset exception handling.
Driving the RES pin low in clock mode 0, 1, or 3 starts output of the internal clock from the
CKIO pin.
Driving the MRES pin low cancels deep standby mode and causes a transition to the power-on
reset state. After this, driving the MRES pin high initiates power-on reset exception handling.
In clock mode 0, 1, or 3, output of the internal clock from the CKIO pin also starts by driving
the MRES pin high.
Keep the RES or MRES pin low until the clock oscillation has settled.
Rev. 2.00 Mar. 14, 2008 Page 1586 of 1824
REJ09B0290-0200