SH7263 Datasheet, PDF (1730/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
35.4.2 Control Signal Timing
Table 35.7 Control Signal Timing
Conditions: VCC = PLLVCC = USBDVCC = 1.1 to 1.3 V, PVCC = USBDPVCC = 3.0 to 3.6 V,
AVCC = 3.0 to 3.6 V, USBAVCC = 1.1 to 1.3 V, USBAPVCC = 3.0 to 3.6 V,
VSS = PLLVSS = PVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS =
USBAPVSS = 0 V, Ta = −40 to 85 °C
Bφ = 66.66 MHz
Item
RES pulse width
MRES pulse width
NMI pulse width
IRQ pulse width
PINT pulse width
Symbol Min.
t
RESW
t_MRESW
t_NMIW
t_IRQW
t
PINTW
20*¹
20*²
20*³
20*³
20
Max.
—
—
—
—
—
Unit
t
cyc
t_cyc
t_cyc
t_cyc
t
cyc
Figure
Figure 35.9
Figure 35.10
IRQOUT/REFOUT output delay time t
IRQOD
BREQ setup time
t
BREQS
—
100
1/2t + 7 —
cyc
ns Figure 35.11
ns Figure 35.12
BREQ hold time
BACK delay time
t
BREQH
t_BACKD
1/2t + 2 —
ns
cyc
—
1/2t_cyc + 13 ns
Bus buffer off time 1
t_BOFF1
—
15
ns
Bus buffer off time 2
t_BOFF2
—
15
ns
Bus buffer on time 1
t
—
15
ns
BON1
Bus buffer on time 2
t_BON2
—
15
ns
BACK setup time when bus buffer off t
0
—
ns
BACKS
Notes: 1. In standby mode or when the clock multiplication ratio is changed, t_RESW = t_OSC2 (10 ms).
2. In standby mode, t = t (10 ms).
MRESW
OSC2
3. In standby mode, t /t = t (10 ms).
NMIW IRQW
OSC3
Rev. 2.00 Mar. 14, 2008 Page 1696 of 1824
REJ09B0290-0200