SH7263 Datasheet, PDF (99/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Operation
Classification Types Code
Function
No. of
Instructions
Floating-point 19
FSCHG SZ bit inversion
48
instructions
FSQRT Floating-point square root
FSTS
Floating-point store from system register FPUL
FSUB
Floating-point subtraction
FTRC
Floating-point conversion with rounding to
integer
FPU-related 2
LDS
Load into floating-point system register
8
CPU
instructions
STS
Store from floating-point system register
Bit
10
BAND
Bit AND
14
manipulation
BCLR
Bit clear
BLD
Bit load
BOR
Bit OR
BSET
Bit set
BST
Bit store
BXOR
Bit exclusive OR
BANDNOT Bit NOT AND
BORNOT Bit NOT OR
BLDNOT Bit NOT load
Total:
112
253
Rev. 2.00 Mar. 14, 2008 Page 65 of 1824
REJ09B0290-0200