SH7263 Datasheet, PDF (1288/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
15
BVAL
0
R/W*¹ Buffer Memory Valid Flag
Writing 1 to this bit is valid when the direction of data
packet is the transmitting direction (when data is
being written to the buffer memory). When the
direction is set to the receiving direction, this bit
should be cleared to 0.
0: Invalid
1: Writing ended
14
BCLR
0
R/W*² CPU Buffer Clear*³
This bit should be used to clear the buffer with this bit
with the pipe invalid state by the pipe configuration
(PID = NAK).
0: Invalid
1: Clears the buffer memory on the CPU side.
13
FRDY
0
R
FIFO Port Ready
Confirming the FIFO port state by reading this bit
requires an access cycle of at least 450 ns after the
pipe has been selected.
0: FIFO port access is disabled.
1: FIFO port access is enabled.
12
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
11 to 0 DTLN[11:0] H'000 R
Receive Data Length*⁴
The length of the receive data can be confirmed.
Notes: 1. Only 1 can be written to.
2. Only reading 0 and writing 1 are valid.
3. The BCLR bit is only valid for the buffer memory on the CPU side when a pipe other
than DCP has been selected. Set BCLR to 1 after confirming that FRDY is 1. When
DCP is selected as a pipe, the buffer memory on the SIE side is also cleared. In this
case, confirming that FRDY = 1 is not necessary.
4. The DTLN bits are only valid for the buffer memory on the CPU side. Confirm that
FRDY = 1 before checking the DTLN bit.
Rev. 2.00 Mar. 14, 2008 Page 1254 of 1824
REJ09B0290-0200