SH7263 Datasheet, PDF (1760/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
CKIO
A25 to A0
A12/A11^*1
CSn
RD/WR
RASU/L
CASU/L
Tp
Tpw
Trr
t_AD1
t_AD1
t_AD1
t_AD1
t_CSD1
t_CSD1
t_CSD1
t_CSD1
t_RWD1
t_RWD1
t_RASD1
t_RASD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
Trc
Trc
Trc
t_RWD1
DQMxx
D31 to D0
(Hi-Z)
BS
CKE
t_CKED1
t_CKED1
DACKn
TENDn^*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 35.37 Synchronous DRAM Self-Refreshing Timing
(WTRP = 1 Cycle)
Rev. 2.00 Mar. 14, 2008 Page 1726 of 1824
REJ09B0290-0200