SH7263 Datasheet, PDF (1230/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
19, 18 ADRCNT 00
[1:0]
R/W Address Issue Byte Count Specification [1:0]
Specify the number of bytes for the address data to be
issued in address stage.
00: Issue 1-byte address
01: Issue 2-byte address
10: Issue 3-byte address
11: Issue 4-byte address
17
DOCMD2 0
R/W Second Command Stage Execution Specification
Specifies whether or not the second command stage is
executed in command access mode.
0: Does not execute the second command stage
1: Executes the second command stage
16
DOCMD1 0
R/W First Command Stage Execution Specification
Specifies whether or not the first command stage is
executed in command access mode.
0: Does not execute the first command stage
1: Executes the first command stage
15 to 0 SCTCNT All 0
[15:0]
R/W Sector Transfer Count Specification [15:0]
Specify the number of sectors to be read continuously
in sector access mode. These bits are counted down
for each sector transfer end and stop when they reach
0.
These bits are used together with SCTCNT[19:16].
In command access mode, these bits are H'0 0001.
Rev. 2.00 Mar. 14, 2008 Page 1196 of 1824
REJ09B0290-0200