SH7263 Datasheet, PDF (311/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
19
MPXMD
0
R/W Burst MPX-I/O Interface Mode Specification
Specify the access mode in 16-byte access
0: One 4-burst access by 16-byte transfer
1: Two 2-burst access cycles by quadword (8-byte)
transfer
Transfer size when MPXMD = 0:
D31 D30 D29 Transfer Size
0
0
0
Byte (1 byte)
0
0
1
Word (2 bytes)
0
1
0
Longword (4 bytes)
0
1
1
Reserved (quadword) (8 bytes)
1
0
0
16 bytes
1
0
1
Reserved (32 bytes)
1
1
0
Reserved (64 bytes)
Transfer size when MPXMD = 1:
D31 D30 D29 Transfer Size
0
0
0
Byte (1 byte)
0
0
1
Word (2 bytes)
0
1
0
Longword (4 bytes)
0
1
1
Quadword (8 bytes)
1
0
0
Reserved (32 bytes)
18
⎯
0
17, 16 BW[1:0]
00
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted at the
second or subsequent access cycles in burst access
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
Rev. 2.00 Mar. 14, 2008 Page 277 of 1824
REJ09B0290-0200