SH7263 Datasheet, PDF (1285/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
4, 3
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2 to 0 CURPIPE[2:0] 000
R/W FIFO Port Access Pipe Specification*²
000: DCP
100: Pipe 4
001: Pipe 1
101: Pipe 5
010: Pipe 2
110: Pipe 6
011: Pipe 3
111: Pipe 7
Notes: 1. Only reading 0 and writing 1 are valid.
2. Changing the values of the ISEL bit and CURPIPE bits in succession requires an
access cycle lasting a minimum of 120 ns plus five bus cycles.
(2) D0FIFOSEL, D1FIFOSEL
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RCNT REW DCLRM DREQE MBW[1:0] TRENB TRCLR DEZPM -
-
-
-
CURPIPE[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W*¹ R/W R/W R/W R/W R/W R/W*¹ R/W R
R
R
R R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
15
RCNT
0
R/W Read Count Mode
0: The DTLN bit is cleared when all of the receive
data has been read.
14
REW
1: The DTLN bit is decremented when the receive
data is read.
0
R/W*¹ Buffer Pointer Rewind
0: Invalid
1: The buffer pointer is rewound.
13
DCLRM
0
R/W Auto Buffer Memory Clear Mode Accessed after
Specified Pipe Data is Read
This bit is valid when the receiving direction (reading
from the buffer memory) has been set for the pipe
specified by the CURPIPE bits.
0: Auto buffer clear mode is disabled.
1: Auto buffer clear mode is enabled.
Rev. 2.00 Mar. 14, 2008 Page 1251 of 1824
REJ09B0290-0200