SH7263 Datasheet, PDF (1001/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
Bit 15 — Enable Timer: When this bit is set, the timer TCNTR is running. When this bit is
cleared, TCNTR and CCR are cleared.
Bit15: TTCR0 15
0
1
Description
Timer and CCR are cleared and disabled (initial value)
Timer is running
Bit 14 — TimeStamp value: Specifies if the Timestamp for transmission and reception in
Mailboxes 15 to 1 must contain the Cycle Time (CYCTR) or the concatenation of CCR[5:0] +
CYCTR[15:6]. This feature is very useful for time triggered transmission to monitor Rx_Trigger.
This register does not affect the TimeStamp for Mailboxes 30 and 31.
Bit14: TTCR0 14
0
1
Description
CYCTR[15:0] is used for the TimeStamp in Mailboxes 15 to 1 (initial value)
CCR[5:0] + CYCTR[15:6] is used for the TimeStamp in Mailboxes 15 to 1
Bit 13 — Cancellation by TCMR2: The messages in the transmission queue are cancelled by
setting TXCR, when both this bit and bit12 are set and compare match occurs when RCAN-TL1 is
not in the Halt status, causing the setting of all TXCR bits with the corresponding TXPR bits set.
Bit13: TTCR0 13
0
1
Description
Cancellation by TCMR2 compare match is disabled (initial value)
Cancellation by TCMR2 compare match is enabled
Bit 12 — TCMR2 compare match enable: When this bit is set, IRR11 is set by TCMR2
compare match.
Bit12 TTCR0 12
0
1
Description
IRR11 isn't set by TCMR2 compare match (initial value)
IRR11 is set by TCMR2 compare match
Rev. 2.00 Mar. 14, 2008 Page 967 of 1824
REJ09B0290-0200