SH7263 Datasheet, PDF (1834/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
Page Revision (See Manual for Details)
25.3.7 FIFO Port Select 1250
Registers (CFIFOSEL,
D0FIFOSEL,
D1FIFOSEL)
(1) CFIFOSEL
(2) D0FIFOSEL,
D1FIFOSEL
1251
Note added
Notes: 1. Only reading 0 and writing 1 are valid.
2. Changing the values of the ISEL bit and CURPIPE
bits in succession requires an access cycle lasting
a minimum of 120 ns plus five bus cycles.
Bit table amended
Bit: 15 14 13 12 11 10 9
8
RCNT REW DCLRM DREQE MBW[1:0] TRENB TRCLR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W*¹ R/W R/W R/W R/W R/W R/W*¹
1251 to
1253
Table amended
Initial
Bit
Bit Name
Value R/W
14
REW
0
R/W*¹
11, 10 MBW[1:0]
0
R/W
8
TRCLR
0
R/W*¹
2 to 0 CURPIPE[2:0] 000 R/W
Description
Buffer Pointer Rewind
0: Invalid
1: The buffer pointer is rewound.
FIFO Port Access Bit Width
00: 8-bit width
01: 16-bit width
10: 32-bit width
11: Setting prohibited
When the selected CURPIPE is set to the buffer
memory read direction, set these bits and the
CURPIPE bits simultaneously.
For details, see 25.4.4, Buffer Memory.
Note: Once reading from the buffer memory is
started, the access bit width of the FIFO port
cannot be changed until all of the data has
been read. Also, the bit width cannot be
changed from the 8-bit width to the 16-/32-bit
width or from the 16-bit width to the 32-bit width
while data is being written to the buffer
memory.
Transaction Counter Clear
This bit is valid when the receiving direction (reading
from the buffer memory) has been set for the pipe
specified by the CURPIPE bits.
0: Invalid
1: The current count is cleared.
FIFO Port Access Pipe Specification*²
000: Not specified
001: PIPE1
010 PIPE2
011: PIPE3
100: PIPE4
101: PIPE5
110: PIPE6
111: PIPE7
Rev. 2.00 Mar. 14, 2008 Page 1800 of 1824
REJ09B0290-0200