SH7263 Datasheet, PDF (1227/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
11, 10 ACM[1:0] 00
R/W Access Mode Specification 1 and 0
Specify access mode.
00: Command access mode
01: Sector access mode
10: Setting prohibited
11: Setting prohibited
9
NANDWF 0
R/W NAND Wait Insertion Operation
0: Performs address or data input/output in one FCLK
cycle
1: Performs address or data input/output in two FCLK
cycles
8 to 4 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
CE
0
R/W Chip Enable
0: Disables the chip (Outputs high level to the FCE pin)
1: Enables the chip (Outputs low level to the FCE pin)
2, 1
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
TYPESEL 0
R/W Memory Select
0: AND-type flash memory is selected
1: NAND-type flash memory or AG-AND is selected
Rev. 2.00 Mar. 14, 2008 Page 1193 of 1824
REJ09B0290-0200