SH7263 Datasheet, PDF (441/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
10.3.8 DMA Operation Register (DMAOR)
The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the
priority level of channels at the DMA transfer. This register also shows the DMA transfer status.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
CMS[1:0]
-
-
PR[1:0]
-
-
-
-
-
AE NMIF DME
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R R/W R/W R
R R/W R/W R
R
R
R
R R/(W)* R/(W)* R/W
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit
15, 14
Bit Name
⎯
13, 12 CMS[1:0]
11, 10 ⎯
Initial
Value
All 0
00
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Cycle Steal Mode Select
These bits select either normal mode or intermittent
mode in cycle steal mode.
It is necessary that the bus modes of all channels be
set to cycle steal mode to make the intermittent mode
valid.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
Executes one DMA transfer for every 16 cycles of
Bφ clock.
11: Intermittent mode 64
Executes one DMA transfer for every 64 cycles of
Bφ clock.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 407 of 1824
REJ09B0290-0200