SH7263 Datasheet, PDF (1239/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value
19
AC1CLR 0
18
AC0CLR 0
17
DREQ1EN 0
16
DREQ0EN 0
15 to 10 —
All 0
R/W
R/W
R/W
R/W
R/W
R
Description
FLECFIFO Clear
Clears FLECFIFO. When changing the read/write
direction, clear the FIFO.
0: Retains the FLECFIFO value. In flash-memory
access, this bit should be cleared to 0.
1: Clears FLECFIFO. After FLECFIFO has been
cleared, this bit should be cleared to 0.
FLDTFIFO Clear
Clears FLDTFIFO. When changing the read/write
direction, clear the FIFO.
0: Retains the FLDTFIFO value. In flash-memory
access, this bit should be cleared to 0.
1: Clears FLDTFIFO. After FLDTFIFO has been
cleared, this bit should be cleared to 0.
FLECFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLECFIFO.
0: Disables the DMA transfer request issued from
FLECFIFO
1: Enables the DMA transfer request issued from
FLECFIFO
FLDTFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLDTFIFO.
0: Disables the DMA transfer request issued from the
FLDTFIFO
1: Enables the DMA transfer request issued from the
FLDTFIFO
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1205 of 1824
REJ09B0290-0200