SH7263 Datasheet, PDF (1280/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
8
FEND
0
R/W FIFO Port Endian
Specifies the byte endian for use in access to the
FIFO port. Tables 25.5 to 25.7 show endian
operation. This LSI operates in big endian. Set this
bit to transmit or receive data with different endians.
7 to 4 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3 to 0 FWAIT[3:0] All 1
R/W FIFO Port Access Wait Specification
These bits specify the number of access waits for the
corresponding FIFO port. The minimum number of
FIFO port access cycles is two.
0000: 0 wait (two access cycles)
:
:
0010: 2 waits (four access cycles)
:
:
0100: 4 waits (six access cycles)
:
:
1111: 15 waits (seventeen access cycles)
:
:
Note: The TEND bit is available only in D0FBCFG and D1FBCFG.
Rev. 2.00 Mar. 14, 2008 Page 1246 of 1824
REJ09B0290-0200