SH7263 Datasheet, PDF (1429/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
Initial
Bit
Bit Name Value R/W Description
7
OFFE3
0
R/W LCDC Power-Off Sequence Period
6
OFFE2
0
R/W Set the period from LCD_VEPWC negation to stopping
5
OFFE1
0
R/W ^{output of the display data (LCD_DATA) and timing}
signals (LCD_FLM, LCD_CL1, LCD_CL2, and
4
OFFE0
0
R/W _{LCD_M_DISP) in the power-off sequence of the LCD}
module in frame units.
Specify to the value of (the period)-1.
This period is the (e) period in figures 26.4 to 26.7,
Power-Supply Control Sequence and States of the LCD
Module.
3
OFFF3
1
R/W LCDC Power-Off Sequence Period
2
OFFF2
1
R/W Set the period from stopping output of the display data
1
OFFF1
1
R/W ^{(LCD_DATA) and timing signals (LCD_FLM, LCD_CL1,}
LCD_CL2, and LCD_M_DISP) to LCD_VCPWC
0
OFFF0
1
R/W _{negation to in the power-off sequence of the LCD}
module in frame units.
Specify to the value of (the period)-1.
This period is the (f) period in figures 26.4 to 26.7,
Power-Supply Control Sequence and States of the LCD
Module.
Rev. 2.00 Mar. 14, 2008 Page 1395 of 1824
REJ09B0290-0200