SH7263 Datasheet, PDF (1845/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
Page
35.4.3 Bus Timing
1704
Figure 35.13 Basic Bus
Timing for Normal Space
(No Wait)
Figure 35.14 Basic Bus 1705
Timing for Normal Space
(One Software Wait
Cycle)
Figure 35.15 Basic Bus 1706
Timing for Normal Space
(One External Wait
Cycle)
Figure 35.16 Basic Bus 1707
Timing for Normal Space
(One Software Wait
Cycle, External Wait
Cycle Valid (WM Bit = 0),
No Idle Cycle)
Figure 35.17 MPX-I/O 1708
Interface Bus Cycle
(Three Address Cycles,
One Software Wait
Cycle, One External Wait
Cycle)
Revision (See Manual for Details)
Figure amended
CSn
Figure amended
t_CSD1
t_CS
CSn
t_CSD1
t_CS
Figure amended
CSn
t_CSD1
t_CS
Figure amended
t_CSD1
CSn
t_CS
t_CSD1
t_CSD1
t_CS
Figure amended
AH
t_AHD
t_AHD
t_AHD
Read
RD
D15 to D0
WE1, WE0
Write
D15 to D0
t_RSD
t_MAD
t_AWH
Address
t_MAH
t_WED1
t_MAD
t_WDD1
t_MAH
t_AWH
Address
t_CSD1
t_CSD1
t_CSD1
t_CSD1
Data
t_RSD
t_RDH1
t_RDS1
Data
t_WED1
t_WDH4
t_WDH1
Rev. 2.00 Mar. 14, 2008 Page 1811 of 1824
REJ09B0290-0200