SH7263 Datasheet, PDF (884/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
Slave receive
mode
SCL
(Master output)
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
TDRE
Slave transmit
mode
9
1
2
3
4
5
6
7
8
9
1
A
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
TEND
TRS
ICDRT
Data 1
Data 2 Data 3
ICDRS
Data 1
Data 2
ICDRR
User
processing ^{[2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2)}
[2] Write data to ICDRT (data 3)
Figure 17.9 Slave Transmit Mode Operation Timing (1)
Rev. 2.00 Mar. 14, 2008 Page 850 of 1824
REJ09B0290-0200