SH7263 Datasheet, PDF (1549/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 Pin Function Controller (PFC)
29.2.12 SSI Oversampling Clock Selection Register (SCSR)
SCSR is a 16-bit readable/writable register that selects the clock source and division ratio of
oversampling clock used in the SSI.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
SSI3CKS[2:0]
-
SSI2CKS[2:0]
-
SSI1CKS[2:0]
-
SSI0CKS[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12 SSI3CKS 000
[2:0]
R/W SSI ch3 Clock Select
Select the source of the oversampling clock that is
used in channel 3 of the SSI. For settings, see table
29.8.
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8 SSI2CKS 000
[2:0]
R/W SSI ch2 Clock Select
Select the source of the oversampling clock that is
used in channel 2 of the SSI. For settings, see table
29.8.
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4 SSI1CKS 000
[2:0]
R/W SSI ch1 Clock Select
Select the source of the oversampling clock that is
used in channel 1 of the SSI. For settings, see table
29.8.
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1515 of 1824
REJ09B0290-0200