SH7263 Datasheet, PDF (278/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value
21 to 19 IWRRD[2:0] 011
18 to 16 IWRRS[2:0] 011
15
⎯
0
R/W Description
R/W Idle Cycles for Read-Read in Another Space
Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
space. The target cycle is a read-read cycle of which
continuous access cycles switch between different
space.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
R/W Idle Cycles for Read-Read in the Same Space
Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
space. The target cycle is a read-read cycle of which
continuous access cycles are for the same space.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 244 of 1824
REJ09B0290-0200