SH7263 Datasheet, PDF (462/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
(b) Single Address Mode
In single address mode, both the transfer source and destination are external devices, either of
them is accessed (selected) by the DACK signal, and the other device is accessed by an address. In
this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external
devices by outputting the DACK transfer request acknowledge signal to it, and at the same time
outputting an address to the other device involved in the transfer. For example, in the case of
transfer between external memory and an external device with DACK shown in figure 10.7, when
the external device outputs data to the data bus, that data is written to the external memory in the
same bus cycle.
This LSI
External address bus External data bus
DMAC
External
memory
External device
with DACK
DACK
DREQ
Data flow (from memory to device)
Data flow (from device to memory)
Figure 10.7 Data Flow in Single Address Mode
Two kinds of transfer are possible in single address mode: (1) transfer between an external device
with DACK and a memory-mapped external device, and (2) transfer between an external device
with DACK and external memory. In both cases, only the external request signal (DREQ) is used
for transfer requests.
Rev. 2.00 Mar. 14, 2008 Page 428 of 1824
REJ09B0290-0200