SH7263 Datasheet, PDF (1509/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 29 Pin Function Controller (PFC)
29.2.5 Port D I/O Register L (PDIORL)
PDIORL is a 16-bit readable/writable register that is used to set the pins on port D as inputs or
outputs. The PD15IOR to PD0IOR bits correspond to the PD15/D31/PINT7/SD_WP/ADTRG/
TIOC4D to PD0/D16/IRQ0/SSCK0/DREQ2/TIOC0A pins, respectively. PDIORL is enabled
when the port D pins are functioning as general-purpose inputs/outputs (PD15 to PD0) or the
TIOC pin is functioning as inputs/outputs of MTU2. In other states, PDIORL is disabled. If a bit
in PDIORL is set to 1, the corresponding pin on port D functions as an output. If it is cleared to 0,
the corresponding pin functions as an input.
Bit:
Initial value:
R/W:
15
PD15
IOR
0
R/W
14
PD14
IOR
0
R/W
13
PD13
IOR
0
R/W
12
PD12
IOR
0
R/W
11
PD11
IOR
0
R/W
10
PD10
IOR
0
R/W
9
PD9
IOR
0
R/W
8
PD8
IOR
0
R/W
7
PD7
IOR
0
R/W
6
PD6
IOR
0
R/W
5
PD5
IOR
0
R/W
4
PD4
IOR
0
R/W
3
PD3
IOR
0
R/W
2
PC2
IOR
0
R/W
1
PD1
IOR
0
R/W
0
PD0
IOR
0
R/W
29.2.6 Port D Control Registers L1 to L4 (PDCRL1 to PDCRL4)
PDCRL1 to PDCRL4 are 16-bit readable/writable registers that are used to select the functions of
the multiplexed pins on port D.
(1) Port D Control Register L4 (PDCRL4)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
PD15MD[2:0]
-
PD14MD[2:0]
-
PD13MD[2:0]
-
PD12MD[2:0]
Initial value: 0
0
0 0/1* 0
0
0 0/1* 0
0
0 0/1* 0
0
0 0/1*
R/W: R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
Note: * Depends on the operating mode of the LSI.
Initial
Bit
Bit Name Value R/W Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1475 of 1824
REJ09B0290-0200