SH7263 Datasheet, PDF (489/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.2 Timer Mode Register (TMDR)
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register
settings should be changed only when TCNT operation is stopped.
Bit: 7
-
Initial value: 0
R/W: R
6
BFE
0
R/W
5
BFB
0
R/W
4
BFA
0
R/W
3
0
R/W
2
1
MD[3:0]
0
0
R/W R/W
0
0
R/W
Initial
Bit
Bit Name Value R/W Description
7
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
BFE
0
R/W Buffer Operation E
Specifies whether TGRE_0 and TGRF_0 are to operate
in the normal way or to be used together for buffer
operation.
TGRF compare match is generated when TGRF is
used as the buffer register.
In channels 1 to 4, this bit is reserved. It is always read
as 0 and the write value should always be 0.
0: TGRE_0 and TGRF_0 operate normally
1: TGRE_0 and TGRF_0 used together for buffer
operation
Rev. 2.00 Mar. 14, 2008 Page 455 of 1824
REJ09B0290-0200