SH7263 Datasheet, PDF (912/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
18.3.2 Status Register (SSISR)
SSISR consists of status flags indicating the operational status of the SSI module and bits
indicating the current channel numbers and word numbers.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
- DMRQ UIRQ OIRQ IIRQ DIRQ -
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
1
0
Un-
Un-
Un-
Un-
Un-
Un-
Un-
Un-
defined defined defined defined defined defined defined defined
R/W: R
R
R
R R/W* R/W* R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
Un-
defined
Un-
defined
Un-
defined
Un-
defined
Un-
defined
Un-
defined
Un-
defined
Un-
defined
Un-
defined
Un-
defined
Un-
defined
Un-
defined
R/W: R
R
R
R
R
R
R
R
R
R
R
R
Note: * Can be read from or written to. Writing 0 initializes the bit, but writing 1 is ignored.
3
2
CHNO[1:0]
0
0
RR
1
0
SWNO IDST
1
1
RR
Initial
Bit
Bit Name Value R/W Description
31 to 29 —
All 0 R
Reserved
The read value is not guaranteed. The write value
should always be 0.
28
DMRQ
0
R
DMA Request Status Flag
This status flag allows the CPU to recognize the value
of the DMA request pin on the SSI module.
• TRMD = 0 (Receive mode)
If DMRQ = 1, the SSIRDR has unread data.
If SSIRDR is read, DMRQ = 0 until there is new
unread data.
• TRMD = 1 (Transmit mode)
If DMRQ = 1, SSITDR requires data to be written to
continue the transmission to the audio serial bus.
Once data is written to SSITDR, DMRQ = 0 until it
requires further transmit data.
Rev. 2.00 Mar. 14, 2008 Page 878 of 1824
REJ09B0290-0200