SH7263 Datasheet, PDF (25/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

21.3.40 Post-ECC Correction Subheader: Data Type (Byte 23) Data Register
(SHEAD27) ........................................................................................................ 1119
21.3.41 Automatic Buffering Setting Control Register 0(CBUFCTL0) .......................... 1119
21.3.42 Automatic Buffering Start Sector Setting: Minutes Control Register
(CBUFCTL1)...................................................................................................... 1121
21.3.43 Automatic Buffering Start Sector Setting: Seconds Control Register
(CBUFCTL2)...................................................................................................... 1121
21.3.44 Automatic Buffering Start Sector Setting: Frames Control Register
(CBUFCTL3)...................................................................................................... 1122
21.3.45 ISY Interrupt Source Mask Control Register (CROMST0M) ............................ 1123
21.3.46 CD-ROM Decoder Reset Control Register (ROMDECRST)............................. 1124
21.3.47 CD-ROM Decoder Reset Status Register (RSTSTAT) ...................................... 1125
21.3.48 SSI Data Control Register (SSI) ......................................................................... 1125
21.3.49 Interrupt Flag Register (INTHOLD)................................................................... 1128
21.3.50 Interrupt Source Mask Control Register (INHINT)............................................ 1129
21.3.51 CD-ROM Decoder Stream Data Input Register (STRMDIN0) .......................... 1130
21.3.52 CD-ROM Decoder Stream Data Input Register (STRMDIN2) .......................... 1130
21.3.53 CD-ROM Decoder Stream Data Output Register (STRMDOUT0).................... 1131
21.4 Operation ......................................................................................................................... 1132
21.4.1 Endian Conversion for Data in the Input Stream ................................................ 1132
21.4.2 Sync Code Maintenance Function ...................................................................... 1133
21.4.3 Error Correction.................................................................................................. 1138
21.4.4 Automatic Decoding Stop Function.................................................................... 1139
21.4.5 Buffering Format ................................................................................................ 1140
21.4.6 Target-Sector Buffering Function....................................................................... 1142
21.5 Interrupt Sources.............................................................................................................. 1144
21.5.1 Interrupt and DMA Transfer Request Signals .................................................... 1144
21.5.2 Timing of Status Registers Updates.................................................................... 1146
21.6 Usage Notes ..................................................................................................................... 1147
21.6.1 Stopping and Resuming Buffering Alone During Decoding .............................. 1147
21.6.2 When CROMST0 Status Register Bits are Set ................................................... 1147
21.6.3 Link Blocks......................................................................................................... 1148
21.6.4 Stopping and Resuming CD-DSP Operation ...................................................... 1148
21.6.5 Note on Clearing the IREADY Flag ................................................................... 1148
21.6.6 Note on Stream Data Transfer (1)....................................................................... 1149
21.6.7 Note on Stream Data Transfer (2)....................................................................... 1149
Section 22 A/D Converter (ADC)....................................................................1151
22.1 Features............................................................................................................................ 1151
22.2 Input/Output Pins ............................................................................................................. 1153
Rev. 2.00 Mar. 14, 2008 Page xxv of xxxiv
REJ09B0290-0200