SH7263 Datasheet, PDF (1714/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 34 List of Registers
Module Register
Power-On Manual Deep
Software Module
Name Abbreviation Reset
Reset
Standby Standby Standby Sleep
Power-
Down
Modes
STBCR6
DSCTR
DSCTR2
Initialized Retained Initialized Retained ⎯
Initialized Retained Initialized Retained ⎯
Initialized Retained Retained Retained ⎯
Retained
Retained
Retained
DSSSR
Initialized Retained Initialized Retained ⎯
Retained
DSFR
Initialized Retained Retained Retained ⎯
Retained
DSRTR
Initialized*¹⁰ Retained Initialized Retained ⎯
Retained
H-UDI*⁹ SDIR
Retained Retained Initialized Retained Retained Retained
SRC
All registers Initialized Retained Initialized Retained Retained Retained
Notes: 1. Retains the previous value after an internal power-on reset by means of the WDT.
2. The BN3 to BN0 bits are initialized.
3. Flag handling continues.
4. Counting up continues.
5. Transfer operations can be continued.
6. Bits RTCEN and START are retained.
7. Bits BC3 to BC0 are initialized.
8. Since pin states are read out on the port A data register (PADRL) and the port registers,
values in these registers are neither retained nor initialized.
9. Initialized by TRST assertion or in the Test-Logic-Reset state of the TAP controller.
10. Initialized by RES assertion and retains the previous value after an internal power-on
reset by means of the H-UDI reset assert command or by means of the WDT.
Rev. 2.00 Mar. 14, 2008 Page 1680 of 1824
REJ09B0290-0200