SH7263 Datasheet, PDF (1162/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.49 Interrupt Flag Register (INTHOLD)
The interrupt flag register (INTHOLD) consists of various interrupt flags.
Bit: 7
6
5
ISEC ITARG ISY
Initial value: 0
0
0
R/W: R/W R/W R/W
4
IERR
0
R/W
3
2
1
IBUF IREADY -
0
0
0
R/W R/W R/W
0
-
0
R/W
Bit Bit Name
7
ISEC
6
ITARG
5
ISY
4
IERR
3
IBUF
2
IREADY
1, 0 ⎯
Initial
Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
All 0 R/W
Description
ISEC Interrupt Flag
Writing 0 to this bit is only possible after 1 has been read
from it.
ITARG Interrupt Flag
Writing 0 to this bit is only possible after 1 has been read
from it.
ISY Interrupt Flag
Writing 0 to this bit is only possible after 1 has been read
from it.
IERR Interrupt Flag
Writing 0 to this bit is only possible after 1 has been read
from it.
IBUF Interrupt Flag
Writing 0 to this bit is only possible after 1 has been read
from it.
IREADY Interrupt Flag
Writing 0 to this bit is only possible after 1 has been read
from it.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1128 of 1824
REJ09B0290-0200